1. Field of the Invention
The present invention relates to a semiconductor device in which a thickness of a gate oxide film is reduced and an electric field in a drain region is also reduced.
2. Description of the Related Art
In a conventional semiconductor device, an N-type well region and a P-type well region are formed in a P-type silicon substrate. In the N-type well region, a P-channel MOS transistor is formed. In the P-type well region, an N-channel MOS transistor is formed. In this event, as to concentration profiles of the N-type well region and the P-type well region, optimum values thereof are determined by considering junction withstand voltages, junction capacities, short-channel effect suppression and the like of the MOS transistors. This technology is described for instance in Japanese Patent Application Publication No. 2004-104141 (Pages 8 to 9, FIG. 11).
In a conventional semiconductor device, by use of a self-alignment technique using a gate electrode as a mask, a source region and a drain region are formed in a P-type semiconductor substrate. On a channel region between the source and drain regions, a gate oxide film and the gate electrode are formed. Note that the drain region is formed in a DDD (Double Diffusion Drain) structure or in an LDD (Lightly Doped Drain) structure. Moreover, the gate oxide film is formed to be thick from an end of the gate electrode to an electric field maximum point in the drain region. There has been known a technology of improving reliability by reducing changes in MOSFET characteristics such as a shift in a threshold voltage value and deterioration of mutual conductance by use of the structure described above. This technology is described for instance in Japanese Patent Application Publication No. 2001-250941 (Pages 4 to 5, 7 pages, FIGS. 1 to 2).
As described above, in the conventional semiconductor device, the N-type well region and the P-type well region are formed in the P-type silicon substrate. Moreover, on the same substrate, the P-channel MOS transistor and the N-channel MOS transistor are formed. In the N-type well region and the P-type well region, the concentration profiles thereof are determined by considering the short-channel effect suppression and the like. Thus, in order to suppress the short-channel effect, it is required to keep impurity concentrations on surfaces of the well regions described above to be high within a desired range. In the case where the drain region is in a SD (Single Drain) structure or in the DDD structure by use of the structure described above, an impurity concentration of a drain diffusion layer is set low and diffusion cannot be expanded. Thus, there is a problem that it is difficult to achieve electric field relaxation in the drain region. Meanwhile, in the case where the drain region is in the LDD structure, an additional step is required, such as formation of a spacer insulating film on a sidewall of a gate electrode. As a result, there is a problem that the number of masks is increased and manufacturing costs are also increased.
Moreover, in the conventional semiconductor device, in order to form a CMOS transistor on the same substrate, a P-type well region is formed in an N-type well region. Moreover, in the N-type and P-type well regions, for the purpose of the short-channel effect suppression and the like, impurities are ion-implanted into'the channel region. Thus, an impurity concentration in a surface region of a semiconductor layer is controlled. With the structure described above, an impurity concentration in a region in which the drain region is formed is relatively high, and diffusion of the drain region is hardly expanded either in a channel direction or in a depth direction. Thus, an electron current density in the drain region is increased, and an ON operation of a parasitic NPN transistor is easily performed. Consequently, there is a problem that withstand voltage characteristics in an ON operation of the semiconductor device are deteriorated.
Moreover, in the conventional semiconductor device, there is a tendency that a thickness of the gate oxide film is reduced or a channel length is shortened, in order to operate the device at a low drive voltage. Moreover, the structure described above induces the shift in the threshold voltage value and lowering of the mutual conductance by hot electron injection. As measures against the above problem, the gate oxide film in a region where characteristics are most affected by hot electrons is formed to be thicker than that in the other regions. However, in order to form the gate oxide film to be thick only in a desired region, dedicated etching and thermal oxidation steps are required. Thus, there is a problem that a manufacturing process is complicated and manufacturing costs are increased.